Renesas Electronics /R7FA2A1AB /SYSTEM /SNZEDCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SNZEDCR

AGTUNFED=0, AD0UMTED=0, SCI0UMTED=0, AD0MATED=0, DTCNZRED=0, DTCZRED=0

Description

Snooze End Control Register

Fields

AGTUNFED	AGT1 underflow Snooze End Enable 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request
DTCZRED	Last DTC transmission completion Snooze End Enable 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request
DTCNZRED	Not Last DTC transmission completion Snooze End Enable 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request
AD0MATED	AD compare match 0 Snooze End Enable 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request
AD0UMTED	AD compare mismatch 0 Snooze End Enable 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request
Reserved	These bits are read as 00. The write value should be 00.
SCI0UMTED	SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode. 0 (0): Disable the Snooze End request 1 (1): Enable the Snooze End request

Links

()